# Homework 1

Simulate a CMOS inverter using LT spice and 0.18um CMOS process parameters provided here.

The supply voltage is 1.8V

The minimum channel length is 0.18um.

The load capacitance is 20fF.

Input signal is a pulse signal with a rise and fall time (case 1:10ps and case 2:100ps)

A) Using the model parameter calculate the inverter transistor sizes so that Tphl+Tplh is less than 400ps and the logic threshold is the mid supply.

Verify your results via simulation using transient simulation. Adjust the channel widths if necessary.

Show the following graphs Vin(t), Vout(t), IMP(t), IMN(t), ICL(t)

Show the rise and fall time and the propagation delay on the graph.

B) Show the DC transfer function. Plot Vout=f(Vin), IMP=f(Vin), IMN=f(Vin)