An Overview of Academic Projects and Theses

● Academic Projects

PETITO - Fractional-N Frequency Synthesizer

General Description:

Fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for delta-sigma modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking precisely the output frequency to a control voltage.

Design Team: 

Devrim Yilmaz AKSIN, Pinar Basak BASYURT, Hayri Ugur UYANIK, Erdogan Ozgur ATES

Publications:

Aksin, D.Y.; Basyurt, P.B.; Uyanik, H.U.; , "Frequency synthesis using pulse width locked loop," Radio-Frequency Integration Technology, 2009. RFIT 2009. IEEE International Symposium on , vol., no., pp.104-107, Jan. 9 2009-Dec. 11 2009

Photos:

SIMURG - 1A Line Driver

General Description:

SIMURG is low power CMOS dual transceiver designed for MIL-STD-1553 communication bus. It is compliant with MIL-STD-1553A and MIL-STD-1553B. The transmitter of each channel accepts complementary CMOS Machester II bi-phase digital data and differentially drives bus isolation transformer. Each transmit channel can be disabled by a separate inhibit control signal. The receiver section of each channel converts the bi-phase complementary data from the bus to the complementary CMOS data to drive Manchester decoder. Each receiver has a separate enable control signal to force its outputs to logic low. It operates from single 3.3V supply voltage and has a low stand-by current of 1mA.

Design Team: 

Devrim Yilmaz AKSIN, Pinar Basak BASYURT, Hayri Ugur UYANIK

Photos:

● BSc Theses

Second Order Analog Delta Sigma Modulator

General Description:

A second order delta-sigma modulator is analysed, various non-idealities are modeled, their effects are observed and finally a second order delta-sigma modulator is designed in the transistor level.

Design Team: 

Devrim Yilmaz AKSIN, Murat DOGU

Noise Analysis and Simulation of a Two-Step SAR ADC

General Description:

Focuses on the analysis of the effects of electrical noise appearing as a degenerative element on ADC performance, the main focus of the work being a previously designed two-step successive approximation register ADC. The main motivation is to arrive at analytical methods of evaluating switched capacitor circuits to predict the noise characteristics of the sub-blocks that make up the ADC; and correlating the analysis with simulation results utilizing two distinct methods of simulation. 

Design Team: 

Devrim Yilmaz AKSIN, Cagri GURLEYUK

● MSc Theses

Wide Input Signal Range 14 Bits  1 MSPS SAR ADC in 0.35 µm HV CMOS Process

General Description:

A novel high voltage sampling technique is proposed for sampling high voltages with standard supply voltages for integrated circuits. The sampling technique is used to implement a wide input signal range successive approximation register analog to digital converter. Besides the one implemented, the proposed sampling technique can be used to realize other ADCs with different specifications.

Design Team: 

Devrim Yilmaz AKSIN, Ilter OZKAYA

Publications:

• Aksin, D.Y.; Ozkaya, I.; , "25V sampling switch for power management data converters in 0.35µm CMOS with DNMOS," ESSCIRC, 2009. ESSCIRC '09. Proceedings of , vol., no., pp.136-139, 14-18 Sept. 2009

Photos:

● PhD Theses

Small Signal Symbolic Analysis

General Description:

To be released after publication.

General Description:

Focuses on fully integrated voltage, current, time and temperature reference architectures  with high precision low power voltage reference architectures. 

Design Team: 

Devrim Yilmaz AKSIN, Pinar Basak BASYURT

Publications:

 
Photos:

General Description:

General Description:

Design Team: 

Devrim Yilmaz AKSIN, Hayri Ugur UYANIK

Publications:

Photos: