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Unless required differently. Assume the following variabilities.


Parameter Minimum Nominal Maximum Unit
Supply Voltage Range -10 0 10 % of Nominal
Reference Voltage Range -2 0 2 % of Nominal
Bias Current Range -4 0 4 % of Nominal
Temperature Range 0 27 80 C

All process corners.

Every schematic built by a designer should have ITUVLSI_TITLE_x block from ITUVLSIREFLIB. Consult ITU VLSI TITLE BORDER MANUAL for filling detail of the border. Design sign-off will be done only after the title borders are hierarchically and properly filled for any given block.

It is possible to create different view names during the design (such as schematic1, schematic2, etc...) for any purpose (simulation, backup, etc...). But only symbol, schematic and layout cell views are accepted for toplevel schematic. The schematic has to be cleaned hierarchically at the end of the design to guarantee only symbol, schematic or layout views are accessed through out the hierarchy.

Consult with the design lead for the process option and/or available components.

Consult to process specific ITU VLSI PROCESS HELP document for allowed power and ground naming conventions and connections; for forbidden or allowed device connections; for shielding.

Every block should appropriate test modes and related documentation notes on the schematic. The block schematic should have all necessary notes to ease design check, layout design, reliability design, simulation result check, etc...

General purpose blocks such as EXOR or Transmission Gates can be found within the PROJECT_MISC category. If you believe that you need to design such a generic cell and it is not already in the MISC category consult with the design lead to fix the problem.

Follow proper schematic drawing practices for readability of the designed schematic. These practices includes but not limited to: inputs are on the left, outputs are on the right, name connection for bulk pins, straight power supply, ground, bias voltage lines, proper symmetry for symmetrical devices, etc...


Symbol blocks should have a title rectangle displaying the cell name.

The instance name should be displayed.

Pin stub should be set to 1.25

All the input pins should be placed on the left side.

All the output pins should be placed on the right side.

Exception for bottom pin placement can be done but there should be justification.

No exception for top pin placement.

Place Power and ground pins upper left and lower left corner respectively.

Separate Power and ground pins from the rest of the input pins with a rectangle.

Symbol rectangle should include appropriate figures to describe the block functionality


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« January 2019 »