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Library - Category - Block Naming Guidelines

1. LIBRARIES

All the projects have 2 default project libraries.

  1. PROJECTNAME_1p0
  2. PROJECTNAME_SIM

PROJECTNAME_1p0 is the design library. You can have other (your own) design libraries too but only aforementioned two will be accessed by all the project designers. The final version of the design should within PROJECTNAME_1p0 directory.

PROJECTNAME_SIM is the simulation library. All your simulation schematics should be within this library. All your simulations should be repeatable by anybody within the design team.

2. CATEGORIES

All toplevel (system level) blocks in the libraries (design or simulation) have to be categorized within their own category. Category name should be a short acronym representing the block functionality. You can consult with the design lead for an acceptable acronym for your assigned block.

Example: ADC, DAC, DIGCORE, PLL, etc...

Sub blocks within a system level block can also be sub-categorized if necessary. There is no need to categorize if there is only one sub block. Sub-category names also should represent the functionality.

Example: ADC_COMP, PLL_VCO, etc...

TOPLEVEL category is reserved to chip level schematics. But it is possible to create sub_blocks top level category as SUBBLOCK_TOP.

Example: ADC_TOP

There should not be any uncategorized block within PROJECTNAME_1p0 and PROJECTNAME_SIM libraries.

3. BLOCKS (Cells)

The block naming convention should also follow the category naming convention. The block name should start with its related category prefix and should follow with the same suffix convention.

Example: ADC_CAPARRAY

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